Update relaxed simd instructions (bytecodealliance#766)

* Rename f32x4.fnma and f64x4.fnma instructions

* Add relaxed_ prefix to all relaxed instructions

Based on WebAssembly/relaxed-simd#42 (comment)

* Renumber relaxed simd instructions

* Implement i16x8.relaxed_q15mulr_s

* Implement relaxed dot instructions

Author: yurydelendik

crates/wasm-encoder/src/core/code.rs

@@ -766,18 +766,22 @@ pub enum Instruction<'a> {
     I32x4RelaxedTruncSatF32x4U,
     I32x4RelaxedTruncSatF64x2SZero,
     I32x4RelaxedTruncSatF64x2UZero,
-    F32x4Fma,
-    F32x4Fms,
-    F64x2Fma,
-    F64x2Fms,
-    I8x16LaneSelect,
-    I16x8LaneSelect,
-    I32x4LaneSelect,
-    I64x2LaneSelect,
+    F32x4RelaxedFma,
+    F32x4RelaxedFnma,
+    F64x2RelaxedFma,
+    F64x2RelaxedFnma,
+    I8x16RelaxedLaneselect,
+    I16x8RelaxedLaneselect,
+    I32x4RelaxedLaneselect,
+    I64x2RelaxedLaneselect,
     F32x4RelaxedMin,
     F32x4RelaxedMax,
     F64x2RelaxedMin,
     F64x2RelaxedMax,
+    I16x8RelaxedQ15mulrS,
+    I16x8DotI8x16I7x16S,
+    I32x4DotI8x16I7x16AddS,
+    F32x4RelaxedDotBf16x8AddF32x4,
 
     // Atomic instructions (the threads proposal)
     MemoryAtomicNotify { memarg: MemArg },
@@ -2321,71 +2325,87 @@ impl Encode for Instruction<'_> {
             }
             Instruction::I8x16RelaxedSwizzle => {
                 sink.push(0xFD);
-                0xA2u32.encode(sink);
+                0x100u32.encode(sink);
             }
             Instruction::I32x4RelaxedTruncSatF32x4S => {
                 sink.push(0xFD);
-                0xA5u32.encode(sink);
+                0x101u32.encode(sink);
             }
             Instruction::I32x4RelaxedTruncSatF32x4U => {
                 sink.push(0xFD);
-                0xA6u32.encode(sink);
+                0x102u32.encode(sink);
             }
             Instruction::I32x4RelaxedTruncSatF64x2SZero => {
                 sink.push(0xFD);
-                0xC5u32.encode(sink);
+                0x103u32.encode(sink);
             }
             Instruction::I32x4RelaxedTruncSatF64x2UZero => {
                 sink.push(0xFD);
-                0xC6u32.encode(sink);
+                0x104u32.encode(sink);
             }
-            Instruction::F32x4Fma => {
+            Instruction::F32x4RelaxedFma => {
                 sink.push(0xFD);
-                0xAFu32.encode(sink);
+                0x105u32.encode(sink);
             }
-            Instruction::F32x4Fms => {
+            Instruction::F32x4RelaxedFnma => {
                 sink.push(0xFD);
-                0xB0u32.encode(sink);
+                0x106u32.encode(sink);
             }
-            Instruction::F64x2Fma => {
+            Instruction::F64x2RelaxedFma => {
                 sink.push(0xFD);
-                0xCFu32.encode(sink);
+                0x107u32.encode(sink);
             }
-            Instruction::F64x2Fms => {
+            Instruction::F64x2RelaxedFnma => {
                 sink.push(0xFD);
-                0xD0u32.encode(sink);
+                0x108u32.encode(sink);
             }
-            Instruction::I8x16LaneSelect => {
+            Instruction::I8x16RelaxedLaneselect => {
                 sink.push(0xFD);
-                0xB2u32.encode(sink);
+                0x109u32.encode(sink);
             }
-            Instruction::I16x8LaneSelect => {
+            Instruction::I16x8RelaxedLaneselect => {
                 sink.push(0xFD);
-                0xB3u32.encode(sink);
+                0x10Au32.encode(sink);
             }
-            Instruction::I32x4LaneSelect => {
+            Instruction::I32x4RelaxedLaneselect => {
                 sink.push(0xFD);
-                0xD2u32.encode(sink);
+                0x10Bu32.encode(sink);
             }
-            Instruction::I64x2LaneSelect => {
+            Instruction::I64x2RelaxedLaneselect => {
                 sink.push(0xFD);
-                0xD3u32.encode(sink);
+                0x10Cu32.encode(sink);
             }
             Instruction::F32x4RelaxedMin => {
                 sink.push(0xFD);
-                0xB4u32.encode(sink);
+                0x10Du32.encode(sink);
             }
             Instruction::F32x4RelaxedMax => {
                 sink.push(0xFD);
-                0xE2u32.encode(sink);
+                0x10Eu32.encode(sink);
             }
             Instruction::F64x2RelaxedMin => {
                 sink.push(0xFD);
-                0xD4u32.encode(sink);
+                0x10Fu32.encode(sink);
             }
             Instruction::F64x2RelaxedMax => {
                 sink.push(0xFD);
-                0xEEu32.encode(sink);
+                0x110u32.encode(sink);
+            }
+            Instruction::I16x8RelaxedQ15mulrS => {
+                sink.push(0xFD);
+                0x111u32.encode(sink);
+            }
+            Instruction::I16x8DotI8x16I7x16S => {
+                sink.push(0xFD);
+                0x111u32.encode(sink);
+            }
+            Instruction::I32x4DotI8x16I7x16AddS => {
+                sink.push(0xFD);
+                0x111u32.encode(sink);
+            }
+            Instruction::F32x4RelaxedDotBf16x8AddF32x4 => {
+                sink.push(0xFD);
+                0x111u32.encode(sink);
             }
 
             // Atmoic instructions from the thread proposal

crates/wasm-mutate/src/mutators/translate.rs

@@ -839,18 +839,22 @@ pub fn op(t: &mut dyn Translator, op: &Operator<'_>) -> Result<Instruction<'stat
         O::I32x4RelaxedTruncSatF32x4U => I::I32x4RelaxedTruncSatF32x4U,
         O::I32x4RelaxedTruncSatF64x2SZero => I::I32x4RelaxedTruncSatF64x2SZero,
         O::I32x4RelaxedTruncSatF64x2UZero => I::I32x4RelaxedTruncSatF64x2UZero,
-        O::F32x4Fma => I::F32x4Fma,
-        O::F32x4Fms => I::F32x4Fms,
-        O::F64x2Fma => I::F64x2Fma,
-        O::F64x2Fms => I::F64x2Fms,
-        O::I8x16LaneSelect => I::I8x16LaneSelect,
-        O::I16x8LaneSelect => I::I16x8LaneSelect,
-        O::I32x4LaneSelect => I::I32x4LaneSelect,
-        O::I64x2LaneSelect => I::I64x2LaneSelect,
+        O::F32x4RelaxedFma => I::F32x4RelaxedFma,
+        O::F32x4RelaxedFnma => I::F32x4RelaxedFnma,
+        O::F64x2RelaxedFma => I::F64x2RelaxedFma,
+        O::F64x2RelaxedFnma => I::F64x2RelaxedFnma,
+        O::I8x16RelaxedLaneselect => I::I8x16RelaxedLaneselect,
+        O::I16x8RelaxedLaneselect => I::I16x8RelaxedLaneselect,
+        O::I32x4RelaxedLaneselect => I::I32x4RelaxedLaneselect,
+        O::I64x2RelaxedLaneselect => I::I64x2RelaxedLaneselect,
         O::F32x4RelaxedMin => I::F32x4RelaxedMin,
         O::F32x4RelaxedMax => I::F32x4RelaxedMax,
         O::F64x2RelaxedMin => I::F64x2RelaxedMin,
         O::F64x2RelaxedMax => I::F64x2RelaxedMax,
+        O::I16x8RelaxedQ15mulrS => I::I16x8RelaxedQ15mulrS,
+        O::I16x8DotI8x16I7x16S => I::I16x8DotI8x16I7x16S,
+        O::I32x4DotI8x16I7x16AddS => I::I32x4DotI8x16I7x16AddS,
+        O::F32x4RelaxedDotBf16x8AddF32x4 => I::F32x4RelaxedDotBf16x8AddF32x4,
 
         // Note that these cases are not supported in `wasm_encoder` yet,
         // and in general `wasmparser` often parses more things than

crates/wasm-smith/src/core/code_builder.rs

@@ -545,13 +545,17 @@ instructions! {
     (Some(simd_v128_on_stack_relaxed), i32x4_relaxed_trunc_sat_f64x2s_zero, Vector),
     (Some(simd_v128_on_stack_relaxed), i32x4_relaxed_trunc_sat_f64x2u_zero, Vector),
     (Some(simd_v128_v128_v128_on_stack_relaxed), f32x4_fma, Vector),
-    (Some(simd_v128_v128_v128_on_stack_relaxed), f32x4_fms, Vector),
+    (Some(simd_v128_v128_v128_on_stack_relaxed), f32x4_fnma, Vector),
     (Some(simd_v128_v128_v128_on_stack_relaxed), f64x2_fma, Vector),
-    (Some(simd_v128_v128_v128_on_stack_relaxed), f64x2_fms, Vector),
+    (Some(simd_v128_v128_v128_on_stack_relaxed), f64x2_fnma, Vector),
     (Some(simd_v128_v128_on_stack_relaxed), f32x4_relaxed_min, Vector),
     (Some(simd_v128_v128_on_stack_relaxed), f32x4_relaxed_max, Vector),
     (Some(simd_v128_v128_on_stack_relaxed), f64x2_relaxed_min, Vector),
     (Some(simd_v128_v128_on_stack_relaxed), f64x2_relaxed_max, Vector),
+    (Some(simd_v128_v128_on_stack_relaxed), i16x8_relaxed_q15mulr_s, Vector),
+    (Some(simd_v128_v128_on_stack_relaxed), i16x8_dot_i8x16_i7x16_s, Vector),
+    (Some(simd_v128_v128_v128_on_stack_relaxed), i32x4_dot_i8x16_i7x16_add_s, Vector),
+    (Some(simd_v128_v128_v128_on_stack_relaxed), f32x4_relaxed_dot_bf16x8_add_f32x4, Vector),
 }
 
 pub(crate) struct CodeBuilderAllocations {
@@ -3956,15 +3960,22 @@ simd_unop!(
     I32x4RelaxedTruncSatF64x2UZero,
     i32x4_relaxed_trunc_sat_f64x2u_zero
 );
-simd_ternop!(F32x4Fma, f32x4_fma);
-simd_ternop!(F32x4Fms, f32x4_fms);
-simd_ternop!(F64x2Fma, f64x2_fma);
-simd_ternop!(F64x2Fms, f64x2_fms);
-simd_ternop!(I8x16LaneSelect, i8x16_laneselect);
-simd_ternop!(I16x8LaneSelect, i16x8_laneselect);
-simd_ternop!(I32x4LaneSelect, i32x4_laneselect);
-simd_ternop!(I64x2LaneSelect, i64x2_laneselect);
+simd_ternop!(F32x4RelaxedFma, f32x4_fma);
+simd_ternop!(F32x4RelaxedFnma, f32x4_fnma);
+simd_ternop!(F64x2RelaxedFma, f64x2_fma);
+simd_ternop!(F64x2RelaxedFnma, f64x2_fnma);
+simd_ternop!(I8x16RelaxedLaneselect, i8x16_laneselect);
+simd_ternop!(I16x8RelaxedLaneselect, i16x8_laneselect);
+simd_ternop!(I32x4RelaxedLaneselect, i32x4_laneselect);
+simd_ternop!(I64x2RelaxedLaneselect, i64x2_laneselect);
 simd_binop!(F32x4RelaxedMin, f32x4_relaxed_min);
 simd_binop!(F32x4RelaxedMax, f32x4_relaxed_max);
 simd_binop!(F64x2RelaxedMin, f64x2_relaxed_min);
 simd_binop!(F64x2RelaxedMax, f64x2_relaxed_max);
+simd_binop!(I16x8RelaxedQ15mulrS, i16x8_relaxed_q15mulr_s);
+simd_binop!(I16x8DotI8x16I7x16S, i16x8_dot_i8x16_i7x16_s);
+simd_ternop!(I32x4DotI8x16I7x16AddS, i32x4_dot_i8x16_i7x16_add_s);
+simd_ternop!(
+    F32x4RelaxedDotBf16x8AddF32x4,
+    f32x4_relaxed_dot_bf16x8_add_f32x4
+);

crates/wasmparser/src/binary_reader.rs

@@ -1889,12 +1889,9 @@ impl<'a> BinaryReader<'a> {
             0x9e => visitor.visit_i16x8_extmul_low_i8x16_u(pos),
             0x9f => visitor.visit_i16x8_extmul_high_i8x16_u(pos),
             0xa0 => visitor.visit_i32x4_abs(pos),
-            0xa2 => visitor.visit_i8x16_relaxed_swizzle(pos),
             0xa1 => visitor.visit_i32x4_neg(pos),
             0xa3 => visitor.visit_i32x4_all_true(pos),
             0xa4 => visitor.visit_i32x4_bitmask(pos),
-            0xa5 => visitor.visit_i32x4_relaxed_trunc_sat_f32x4_s(pos),
-            0xa6 => visitor.visit_i32x4_relaxed_trunc_sat_f32x4_u(pos),
             0xa7 => visitor.visit_i32x4_extend_low_i16x8_s(pos),
             0xa8 => visitor.visit_i32x4_extend_high_i16x8_s(pos),
             0xa9 => visitor.visit_i32x4_extend_low_i16x8_u(pos),
@@ -1903,12 +1900,7 @@ impl<'a> BinaryReader<'a> {
             0xac => visitor.visit_i32x4_shr_s(pos),
             0xad => visitor.visit_i32x4_shr_u(pos),
             0xae => visitor.visit_i32x4_add(pos),
-            0xaf => visitor.visit_f32x4_fma(pos),
-            0xb0 => visitor.visit_f32x4_fms(pos),
             0xb1 => visitor.visit_i32x4_sub(pos),
-            0xb2 => visitor.visit_i8x16_laneselect(pos),
-            0xb3 => visitor.visit_i16x8_laneselect(pos),
-            0xb4 => visitor.visit_f32x4_relaxed_min(pos),
             0xb5 => visitor.visit_i32x4_mul(pos),
             0xb6 => visitor.visit_i32x4_min_s(pos),
             0xb7 => visitor.visit_i32x4_min_u(pos),
@@ -1923,8 +1915,6 @@ impl<'a> BinaryReader<'a> {
             0xc1 => visitor.visit_i64x2_neg(pos),
             0xc3 => visitor.visit_i64x2_all_true(pos),
             0xc4 => visitor.visit_i64x2_bitmask(pos),
-            0xc5 => visitor.visit_i32x4_relaxed_trunc_sat_f64x2_s_zero(pos),
-            0xc6 => visitor.visit_i32x4_relaxed_trunc_sat_f64x2_u_zero(pos),
             0xc7 => visitor.visit_i64x2_extend_low_i32x4_s(pos),
             0xc8 => visitor.visit_i64x2_extend_high_i32x4_s(pos),
             0xc9 => visitor.visit_i64x2_extend_low_i32x4_u(pos),
@@ -1933,12 +1923,7 @@ impl<'a> BinaryReader<'a> {
             0xcc => visitor.visit_i64x2_shr_s(pos),
             0xcd => visitor.visit_i64x2_shr_u(pos),
             0xce => visitor.visit_i64x2_add(pos),
-            0xcf => visitor.visit_f64x2_fma(pos),
-            0xd0 => visitor.visit_f64x2_fms(pos),
             0xd1 => visitor.visit_i64x2_sub(pos),
-            0xd2 => visitor.visit_i32x4_laneselect(pos),
-            0xd3 => visitor.visit_i64x2_laneselect(pos),
-            0xd4 => visitor.visit_f64x2_relaxed_min(pos),
             0xd5 => visitor.visit_i64x2_mul(pos),
             0xd6 => visitor.visit_i64x2_eq(pos),
             0xd7 => visitor.visit_i64x2_ne(pos),
@@ -1952,7 +1937,6 @@ impl<'a> BinaryReader<'a> {
             0xdf => visitor.visit_i64x2_extmul_high_i32x4_u(pos),
             0xe0 => visitor.visit_f32x4_abs(pos),
             0xe1 => visitor.visit_f32x4_neg(pos),
-            0xe2 => visitor.visit_f32x4_relaxed_max(pos),
             0xe3 => visitor.visit_f32x4_sqrt(pos),
             0xe4 => visitor.visit_f32x4_add(pos),
             0xe5 => visitor.visit_f32x4_sub(pos),
@@ -1964,7 +1948,6 @@ impl<'a> BinaryReader<'a> {
             0xeb => visitor.visit_f32x4_pmax(pos),
             0xec => visitor.visit_f64x2_abs(pos),
             0xed => visitor.visit_f64x2_neg(pos),
-            0xee => visitor.visit_f64x2_relaxed_max(pos),
             0xef => visitor.visit_f64x2_sqrt(pos),
             0xf0 => visitor.visit_f64x2_add(pos),
             0xf1 => visitor.visit_f64x2_sub(pos),
@@ -1982,6 +1965,27 @@ impl<'a> BinaryReader<'a> {
             0xfd => visitor.visit_i32x4_trunc_sat_f64x2_u_zero(pos),
             0xfe => visitor.visit_f64x2_convert_low_i32x4_s(pos),
             0xff => visitor.visit_f64x2_convert_low_i32x4_u(pos),
+            0x100 => visitor.visit_i8x16_relaxed_swizzle(pos),
+            0x101 => visitor.visit_i32x4_relaxed_trunc_sat_f32x4_s(pos),
+            0x102 => visitor.visit_i32x4_relaxed_trunc_sat_f32x4_u(pos),
+            0x103 => visitor.visit_i32x4_relaxed_trunc_sat_f64x2_s_zero(pos),
+            0x104 => visitor.visit_i32x4_relaxed_trunc_sat_f64x2_u_zero(pos),
+            0x105 => visitor.visit_f32x4_relaxed_fma(pos),
+            0x106 => visitor.visit_f32x4_relaxed_fnma(pos),
+            0x107 => visitor.visit_f64x2_relaxed_fma(pos),
+            0x108 => visitor.visit_f64x2_relaxed_fnma(pos),
+            0x109 => visitor.visit_i8x16_relaxed_laneselect(pos),
+            0x10a => visitor.visit_i16x8_relaxed_laneselect(pos),
+            0x10b => visitor.visit_i32x4_relaxed_laneselect(pos),
+            0x10c => visitor.visit_i64x2_relaxed_laneselect(pos),
+            0x10d => visitor.visit_f32x4_relaxed_min(pos),
+            0x10e => visitor.visit_f32x4_relaxed_max(pos),
+            0x10f => visitor.visit_f64x2_relaxed_min(pos),
+            0x110 => visitor.visit_f64x2_relaxed_max(pos),
+            0x111 => visitor.visit_i16x8_relaxed_q15mulr_s(pos),
+            0x112 => visitor.visit_i16x8_dot_i8x16_i7x16_s(pos),
+            0x113 => visitor.visit_i32x4_dot_i8x16_i7x16_add_s(pos),
+            0x114 => visitor.visit_f32x4_relaxed_dot_bf16x8_add_f32x4(pos),
 
             _ => bail!(pos, "unknown 0xfd subopcode: 0x{code:x}"),
         })

crates/wasmparser/src/lib.rs

@@ -647,18 +647,22 @@ macro_rules! for_each_operator {
             @relaxed_simd I32x4RelaxedTruncSatF32x4U => visit_i32x4_relaxed_trunc_sat_f32x4_u
             @relaxed_simd I32x4RelaxedTruncSatF64x2SZero => visit_i32x4_relaxed_trunc_sat_f64x2_s_zero
             @relaxed_simd I32x4RelaxedTruncSatF64x2UZero => visit_i32x4_relaxed_trunc_sat_f64x2_u_zero
-            @relaxed_simd F32x4Fma => visit_f32x4_fma
-            @relaxed_simd F32x4Fms => visit_f32x4_fms
-            @relaxed_simd F64x2Fma => visit_f64x2_fma
-            @relaxed_simd F64x2Fms => visit_f64x2_fms
-            @relaxed_simd I8x16LaneSelect => visit_i8x16_laneselect
-            @relaxed_simd I16x8LaneSelect => visit_i16x8_laneselect
-            @relaxed_simd I32x4LaneSelect => visit_i32x4_laneselect
-            @relaxed_simd I64x2LaneSelect => visit_i64x2_laneselect
+            @relaxed_simd F32x4RelaxedFma => visit_f32x4_relaxed_fma
+            @relaxed_simd F32x4RelaxedFnma => visit_f32x4_relaxed_fnma
+            @relaxed_simd F64x2RelaxedFma => visit_f64x2_relaxed_fma
+            @relaxed_simd F64x2RelaxedFnma => visit_f64x2_relaxed_fnma
+            @relaxed_simd I8x16RelaxedLaneselect => visit_i8x16_relaxed_laneselect
+            @relaxed_simd I16x8RelaxedLaneselect => visit_i16x8_relaxed_laneselect
+            @relaxed_simd I32x4RelaxedLaneselect => visit_i32x4_relaxed_laneselect
+            @relaxed_simd I64x2RelaxedLaneselect => visit_i64x2_relaxed_laneselect
             @relaxed_simd F32x4RelaxedMin => visit_f32x4_relaxed_min
             @relaxed_simd F32x4RelaxedMax => visit_f32x4_relaxed_max
             @relaxed_simd F64x2RelaxedMin => visit_f64x2_relaxed_min
             @relaxed_simd F64x2RelaxedMax => visit_f64x2_relaxed_max
+            @relaxed_simd I16x8RelaxedQ15mulrS => visit_i16x8_relaxed_q15mulr_s
+            @relaxed_simd I16x8DotI8x16I7x16S => visit_i16x8_dot_i8x16_i7x16_s
+            @relaxed_simd I32x4DotI8x16I7x16AddS => visit_i32x4_dot_i8x16_i7x16_add_s
+            @relaxed_simd F32x4RelaxedDotBf16x8AddF32x4 => visit_f32x4_relaxed_dot_bf16x8_add_f32x4
         }
     };
 }