ise-build

Python build system for Xilinx ISE / Spartan-6 FPGA projects with SystemVerilog support.

Designed to live as a git submodule inside your project. Handles source collection, SystemVerilog-to-Verilog conversion via sv2v, ISE compatibility patching, and the full ISE toolchain (XST → NGDBUILD → MAP → PAR → BITGEN).

Requirements

• Python 3.10+
• Xilinx ISE 14.7
• sv2v (only if your project uses SystemVerilog)

Setup

Add as a git submodule to your project:

git submodule add <this-repo-url> build-script

Edit build-script/config.py to set your device, Xilinx path, and source layout.

Usage

Run from your project root:

python build-script/build.py --build            # compile only
python build-script/build.py --build --release  # compile + save bitstream to releases/
python build-script/build.py --all              # same as above
python build-script/build.py --release          # copy existing .bit to releases/

Expected project layout

my-project/
├── top.sv                  # or top.v — top-level module
├── constraints/
│   └── top.ucf
├── submodules/
│   ├── common/             # flat folder, read directly
│   │   └── utils.sv
│   ├── generated/          # flat folder, read directly
│   │   └── pll.v
│   └── some-ip/            # git submodule repo, only src/ is read
│       └── src/
│           └── mod.sv
└── build-script/           # this repo

Source collection

Location	Rule
top.sv / top.v in project root	Always included first
submodules/<repo>/src/	Included — only the src/ subfolder
submodules/common/, submodules/generated/	Included — read directly (configurable via FLAT_SUBDIRS)
Files matching *_tb.v, tb_*.v, *_test.sv, etc.	Always excluded
build-script/compat/*.v	Prepended before all project sources

ISE compatibility

The following constructs are fixed automatically in the generated all_design.v:

Construct	Fix
$clog2(N)	Replaced with a local clog2() function injected into each module that uses it

Additional simple text replacements can be added to ISE_PATCHES in config.py.

To add more compat helper functions, drop a .v file into compat/ — it will be included in every build automatically.

Configuration

All settings are in build-script/config.py:

XILINX_ROOT = r"C:\Xilinx\14.7\ISE_DS\ISE"  # path to ISE installation
DEVICE      = "xc6slx16-ftg256-3"             # target device
PROJECT_NAME = "top"                           # top module name

SOURCE_SUBDIRS = ["src"]                       # subfolders to read inside submodule repos
FLAT_SUBDIRS   = ["common", "generated"]       # submodules/ folders read directly

TESTBENCH_PATTERNS = ["*_tb.v", "tb_*.v", ...]  # excluded file patterns

ISE_PATCHES = [                                # extra text replacements applied to all_design.v
    # ("description", "old", "new"),
]

Build output

File	Description
build/all_design.v	Merged and patched Verilog (sv2v output)
build/top.bit	Bitstream
build/build_<timestamp>.log	Full build log
releases/top_<timestamp>.bit	Released bitstream (with --release)