spi_transmitter_inst.v

// Copyright (C) 2023  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and any partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details, at
// https://fpgasoftware.intel.com/eula.


// Generated by Quartus Prime Version 22.1 (Build Build 922 07/20/2023)
// Created on Tue Mar 12 16:12:10 2024

spi_transmitter spi_transmitter_inst
(
	.clock(clock_sig) ,	// input  clock_sig
	.reset(reset_sig) ,	// input  reset_sig
	.data(data_sig) ,	// input [23:0] data_sig
	.busy(busy_sig) ,	// input  busy_sig
	.start_transmit(start_transmit_sig) ,	// input  start_transmit_sig
	.sdo(sdo_sig) ,	// output  sdo_sig
	.sclk(sclk_sig) ,	// output  sclk_sig
	.sync_n(sync_n_sig) ,	// output  sync_n_sig
	.reset_n(reset_n_sig) ,	// output  reset_n_sig
	.spi_busy(spi_busy_sig) 	// output  spi_busy_sig
);

defparam spi_transmitter_inst.Wait = 'b00;
defparam spi_transmitter_inst.LoadData = 'b01;
defparam spi_transmitter_inst.Transmission = 'b10;