Fix: yosys flow missed source file after parameter defaults'

update docs

New: JAL execution doesn't wait for anymore processing ready

     CPI = 2.03

Doc update / v1.5.0

Prepare release v1.4.0

Fix: divisor module asserted its ready one cycle earlier, making the RD

     register not updated yet during a back-to-back processing
New: Add printf benchmark

Doc: add details for dCache

New: Finalize AXI-Crossbar integration and pass successfully the

     compliance testsuite

New: Deploy the new trap handling system

    - mtvec now support direct & vectored mode
    - mtval is also written by control unit
    - load/store misalignment is better implemented

New: Moving data interface to AXI4-lite

Change: GPIOs are no more part of the core and will be integrated lated
        within a top level including the interconnect
Change: Testbench uses the same AXI4-lite RAM for data and instruction
Change: AXI4-lite RAM now has two ports
Fix: Fetcher didn't initiated flush procedure if was in IDLE