Commits

History for

Commits on Oct 16, 2021

Change use of blocking assignment to non-blocking inside always_ff

hzeller
authored and
rswarbrick
committed

Commits on Jul 14, 2021

[formal] Read Verilog files in Yosys

towoe
authored and
rswarbrick
committed
[formal] Switch to new top level

towoe
authored and
rswarbrick
committed
Get riscv-formal flow working again
rswarbrick
committed

Commits on Jun 15, 2021

[dv] Fix icache formal tb after recent parameter changes
rswarbrick
committed

Commits on Dec 2, 2020

[rtl] Add branch prediction signals to icache

Tom Roberts
authored and
tomeroberts
committed
[rtl] icache performance updates

Tom Roberts
authored and
tomeroberts
committed
[fpv] Assume icache req_i input is low when in reset

rswarbrick
authored and
tomeroberts
committed

Commits on Sep 16, 2020

[formal] Add check for multdiv cycle consumption

towoe
authored and
rswarbrick
committed
Move sv2v script into standalone core file

towoe
authored and
rswarbrick
committed

Commits on Aug 31, 2020

Port ICache formal core file to final Edalize design
rswarbrick
committed

Commits on Jun 8, 2020

[syn] Update path to prim_assert

Tom Roberts
authored and
tomeroberts
committed
[rtl] Rewrite perf counters to be Yosys compatible

Tom Roberts
authored and
tomeroberts
committed

Commits on May 25, 2020

[formal] Create Ibex Verilog source

towoe
authored and
imphil
committed

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