Self-hosted game stream host for Moonlight.

QARMA block cipher in C

Verilog/SystemVerilog Extension for Zed

ChipWhisperer - the complete open-source toolchain for side-channel power analysis and glitching attacks

A launch point for your personal nvim configuration

Side-Channel Analysis Library

Verilog Hardware Design of Ascon v1.2 with power side-channel mitigations

Qt based visualization for the VeeR RISC-V core [WIP]

Simulate And Synthesize HDLs!

Hugo theme made for blogs

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

Hugo documentation theme as simple as plain book

Ananke: A theme for Hugo Sites

Core interfaces for universal DNS record manipulation across providers

A free standard cell library for SDDS-NCL circuits

Launch an Ubuntu lxc container and install Xilinx Vitis/Vivado

Dockerfile with Vivado for CI

draws an SVG schematic from a JSON netlist

Hardware implementation of Lightweight Cryptography candidates in Bluespec SystemVerilog.

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

UNSUPPORTED INTERNAL toolchain builds

Development Package for the Hardware API for Lightweight Cryptography

A Multithreaded Entity Component System written for C89 & C99

Python Productivity for ZYNQ