VeriFlow-CC: A Claude Code-driven RTL design pipeline. Automates Chip-on-Chat from architecture to synthesis (iVerilog/Yosys) using a stateful, zero-dependency LLM orchestration skill. Features sub-agent nesting for code gen and behavioral-driven verification.

VeriFlow-Agent: Agent-based RTL Design Pipeline A LangGraph-powered RTL design automation tool that transforms hardware design from manual coding to agent-based workflows. Features 7-stage pipeline (Architect → Synthesis), multi-backend LLM support (Claude/Anthropic/LangChain), and three interfaces: Claude Code Agent, Web UI, and CLI.

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A data analyst project that handles data , perform analysis using pandas and for visualization - matplotlib and seaborn but inbuilt with an llm based ai which acts like a brain and morphs the output based on the dataset given.