A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding
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May 20, 2022 - Verilog
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hazard-detection
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Verilog Implementation of an ARM LEGv8 CPU
arm verilog xilinx isa vivado hazard-detection ldr pipeline-cpu single-cycle hennessy patterson legv8-arm multi-cycle arm-legv8-simulator forwarding-unit
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Oct 3, 2018 - Verilog
A python toolbox for easily downloading and processing Sentinel-1 SLC, Sentinel-2 and DEM data.
geospatial insar remote-sensing satellite-imagery hazard-detection sar earth-observation synthetic-aperture-radar interferometry sentinel-2 sentinel-1 analysis-ready
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Jun 10, 2026 - Jupyter Notebook
🧠 This repository features an intelligent agent that autonomously explores the Wumpus World—a grid filled with hidden Wumpuses, pits, and gold. Using logic, inference, and planning, the agent avoids dangers, finds gold, and escapes. Includes real-time Pygame visualization and customizable settings, ideal for AI/game logic study and experimentation
reinforcement-learning decision-making simulation-environment artificial-intelligence game-theory logic-programming hazard-detection educational-game pathfinding-algorithms knowledge-representation autonomous-agents search-strategies inference-engine python-project ai-in-games grid-based-games pygame-visualization agent-reason classic-ai-problem planning-module
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Aug 21, 2025 - Python
Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection, Branch Target Buffer using LRU replacement policy, absolute value custom instruction.
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Apr 12, 2020 - Verilog
An MIPS pipelined processor with hazard detection for the course VE370 (FA2020) at UMJI.
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Dec 28, 2020 - Verilog
A 5-Stage Pipelined RISC-V Processor designed and implemented on FPGA (Artix-7 Nexys A7). Supports RV32I instructions set (R, I, S, B, U, J types) with ALU, control unit, hazard detection, forwarding, and pipeline registers. Verified through simulation and hardware testing with optimized timing and 4× performance gain.
fpga processor systemverilog pipelining computer-architecture hazard-detection risc-v system-design riscv32 datapath-design pipelined-processor control-logic
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Oct 13, 2025 - SystemVerilog
ARM Processor, Computer Architecture laboratory, University of Tehran
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Sep 10, 2021 - Verilog
A pipelined MIPS processor implemented in Verilog, featuring hazard detection and forwarding.
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Sep 13, 2025 - Verilog
Augmented-Waste-Classifier-SigLIP2 is an image classification vision-language encoder model fine-tuned from google/siglip2-base-patch16-224
google image-classification vit hazard-detection hazard-assessment waste-management huggingface-transformers siglip2
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May 25, 2025 - Python
Smart Building Evacuation Ontology
hazard-detection context-aware smartbuildings evacuation-ontology emergency-evacuation sbeo group-based-evacuation people-with-impairments
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Jun 10, 2023
A 32-bit Arm Processor Using Verilog HDL With Hazard Detection, Forwarding Unit, SRAM Memory & A 2-Way Set-Associative Cache.
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Jul 22, 2021 - Verilog
Python GUI-based hazard video labelling
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Jan 29, 2019 - Python
A real-time application for detecting and tracking Globally Harmonized System (GHS) hazard labels using computer vision.
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Mar 26, 2025 - Python
Design and development of a complete RISC CPU with: five stage pipeline, forwarding, automatic hazard detection, BTB using LRU policy replacement, four-cycle hardware multiplier.
cpu mips vhdl microprocessor forwarding computer-architecture hazard-detection risc dlx multiplier branch-predictor digital-electronics btb bht
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Dec 10, 2019 - VHDL
A chemical inventory screening tool to detect and classify chemical hazards in wet labs
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Apr 22, 2026 - Jupyter Notebook
CURSO: Sistemas de Información Geográfica aplicados a Desarrollo y Ordenamiento Territorial (OT) - SIGE
gis urban-planning digital-elevation-model hazard-detection soil-mapping population-dynamics arcgis-pro rural-development urban-development
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Jun 4, 2026 - Python
End-to-end 8-bit, 5-stage pipelined CPU on Nexys A7 (Artix-7) — handwritten Verilog (RTL), MMIO-integrated embedded platform, verified bitstream.
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May 24, 2026 - Verilog
A 5-stage, in order, pipelined upgrade of the single-cycle RV32I CPU in SystemVerilog. Includes the RISC-V "M" extension (multiply/divide) with multi-cycle arithmetic units, a full hazard unit with data forwarding and dynamic branch prediction.
asic cpu fpga pipeline riscv verilog systemverilog computer-architecture hazard-detection branch-prediction multicycle hardware-design
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Dec 8, 2025 - SystemVerilog
A Verilog-based five-stage pipelined processor with complete hazard handling (stalling, forwarding) and modular RTL design.
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Jan 25, 2026 - Verilog
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